フラッシュメモリ制御回路

Flash memory control circuit

Abstract

PROBLEM TO BE SOLVED: To enable a flash memory control circuit to freely set the size of an inhibition program while making an inhibition area not to be limited with a flash memory element in the case of inhibiting a write-in to a specified address by decoding an address signal and inhibiting a voltage control signal or a write control signal needed at a write time only with respect to the specified address. SOLUTION: For example, when a program whose write-in is wanted to inhibit becomes large, a signal is generated only with respect to a specific address in a decoding means 1 and a voltage needed at the write-in is inhibited in a voltage generating means 3 with the signal generated by a voltage control signal generating means 2. Like this, when the write-in to the specific address is inhibited in a system in which a flash memory is used, the free setting of the size of the program is made possible without being limited by the flash memory element by the decoding means 1, the voltage control signal generating means 2 and the voltage generating means 3. COPYRIGHT: (C)1998,JPO
(57)【要約】 【課題】 フラッシュメモリを用いたシステムにおい て、フラッシュメモリ素子によって限定されることな く、書き込みを禁止したいプログラムの大きさを自由に 設定することができるフラッシュメモリ制御回路を提供 するものである。 【解決手段】 デコード手段1によって特定のアドレス に対してのみ信号を発生し、電圧制御信号発生手段2に よって発生した信号により、電圧供給手段3において書 き込み時に必要な電圧を抑止する構成とした。

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